Consumer demand for high performance and low power microchips have been a major driving force behind the continued need for scaling of semiconductor devices. Today’s semiconductor chips face extreme pressure to achieve increased performance, while reducing their size and accommodating new functionalities. When the size of the transistors shrink, interconnect delay and power consumption affects performance adversely. In SoCs (System on a Chip), longer interconnects translate into reduced speed and increased power consumption. Thus continued scaling necessarily requires the introduction of both new materials and new device integration schemes.
Emerging 3D Integration Technology
Three-dimensional (3D) integration is an emerging technology that can form highly integrated systems by vertically stacking and connecting together various materials, technologies and functional components. 3D integration consists of stacking integrated circuits and connecting them vertically so that they behave as a single device. A 3D chip is therefore just a stack of multiple device layers with direct vertical interconnects tunneling through them.
Not only does 3D integration reduce the length of interconnects it also provides higher transistor density, faster interconnects and heterogeneous technology integration, with potentially lower power, cost and faster time-to-market.
The concept of 3D stacking or integration technology is certainly not new. In fact, 3D stacking of dies has been successfully demonstrated and is currently being commercially employed in some embedded domains (for instance, stacking DRAM memory on CPU cores). A recent 3D IC report from Yole Development suggests that by 2012, the number of 3D IC-processed wafers could surpass 10 million units, driven in part by handset, wireless and computing applications.
Other notable applications include DRAM, SRAM and Flash EPROM stacks for mobile devices. Other applications will soon be revealed as the key semiconductor companies make their individual breakthroughs towards commercially viable 3D stacked chips.
Given the intense interest and effort into developing 3D integration technology, the 10 million units prediction seems just about right—assuming, of course, that a few challenges are met. The most important challenge being dissipation of heat built up within the stack. This is an inevitable issue as electrical proximity co-relates with thermal proximity.
Recent Breakthroughs by IBM
IBM has emerged as one of the major player in research in the field of 3D integration of chips. In 2010 IBM declared that its research on 3D chip stacking will take Moore’s Law past 2020. By integrating a very large (SoC) in multiple tiers, the average distance between system components is reduced, which improved both efficiency and performance. However, the challenge to remove the heat generated ,as chip volumes became smaller and smaller, was still a key issue.
IBM’s solution to overheating came in the form of a product named “Aquasar”, a first of a kind, water-cooled supercomputer. In Aquasar, chip-level cooling with a water temperature of approximately 60⁰C was sufficient to keep the chip at operating temperatures well below the maximally allowed 85⁰C. The high input temperature of the coolant results in an even higher-grade heat as an output, which in this case was translated to 65 ⁰C. The entire cooling system was a closed circuit: the cooling water was heated constantly by the chips and consequently cooled to the required temperature as it passed through a passive heat exchanger, thus delivering the removed heat directly to the heating system.
While the Aquasar approach remains yet to be commercially viable and seems unlikely to ever revolutionize consumer electronics, its implications on development of supercomputers are noteworthy. IBM currently holds the pioneer intellectual property in novel methods of 3d-stacking and cooling the system. (Refer patentsUS7990711B1, US7893529B2, US20090290282A1 and US20090251862A1)
In 2011 IBM went a step further and collaborated with 3M to jointly develop a special adhesive which can be used to package semiconductors into densely stacked silicon “towers.”Such stacking would allow for dramatically higher levels of integration for information technology and consumer electronics
A collaboration between IBM and 3M has can easily leapfrog today’s attempts at stacking chips vertically – known as 3D packaging. IBM will draw on its expertise in creating unique semiconductor packaging processes, and 3M will provide its expertise in developing and manufacturing adhesive materials, particularly a new kind of adhesive which densely stack the chips one over the other and at the same time efficiently conduct heat through the densely packed stack of chips, away from heat sensitive components such as logic circuits. This new adhesive is currently being used on 3M’s 46 core technology platforms.IBM in their press release has claimed that this technology will allow it to push microprocessor speeds to 1000 times the current standards.
Moore’s law states that the number of transistors that can be placed inexpensively on an integrated circuit will double every 18 months. More than 50 years old, this law is still in effect, but
to extend it as long as 2020 will require a change from mere transistor scaling to novel packaging architectures such as 3D integration, the vertical integration of chips.
In the coming years we expect integration of 3d chips to be an extremely profitable industry. Any breakthrough in this domain would allow rapid advancement in the mobile phone, tablet, Ultra-mobile PC (processor, memory, ASIC, RF), Digital camera (ASIC, memory), Digital video products (GPU, memory), Imaging sensor module (image sensor, DSP, SRAM) domains.
A recent study by Yole Développement shows that by 2012 the 3d-SiP industry will have an annual growth rate of 251% overtaking other technologies like CIS, Flash, DRAM, MEMS etc which indicates that 3D-Sip will aggressively take up majority of the packaging market share.
Featured image: By iRunway Inc.