The latest buzz in the semiconductor world of consumers is the use of FinFET transistors in their laptops, smartphones and PDAs. With these devices shrinking in size and customers demanding for better power management, electronics majors have entered into a rat race to improve traditional planar transistors such as MOSFETs. This is in an effort to… (Featured image source: https://upload.wikimedia.org/wikipedia/commons/0/02/80486dx2-large.jpg)
The latest buzz in the semiconductor world of consumers is the use of FinFET transistors in their laptops, smartphones and PDAs. With these devices shrinking in size and customers demanding for better power management, electronics majors have entered into a rat race to improve traditional planar transistors such as MOSFETs. This is in an effort to create tri-gate FinFETs that are promising better performance and higher efficiency in plugging power leakage.
FinFET transistors made a cut when Intel began using them for its Ivy-Bridge CPUs back in 2012. The buzz just got bigger when in October 2016 Samsung announced that it had begun mass production of System-on-Chip (SoC) products that were powered with 10nm FinFET technology. While Samsung and other players such as Apple, Global Foundries, HiSilicon were producing FinFETs of 14nm, Samsung’s move to produce 10nm FinFET products made it the first in the industry to be involved in the production of such a mobile application processor.
From MOSFET to FinFET – The evolution curve
One of the prime reasons that makes FinFETs a much scouted for transistor technology in the semiconductor market today is its ability to lower power consumption and plug power leakage. This means that the device can achieve high performance in a low power state. No chip manufacturer will not want to jump towards this technology prowess!
The prime factor that helps FinFET achieve this high level of power management is its 3D pattern. In a planar transistor, the Gate was raised above the power source, which meant a large amount of power was draining away. The FinFET chip has a raised source that gives the Gate larger control over power, reducing the drain and thus powering up active power efficiency by almost 50%.
Spacing between the fins is called fin pitch, and the spacing between interconnect metal modules is called metal pitch. An initial FinFET design is evaluated to find the fin pitch and the metal pitch. From the ratio of the metal pitch and the fin pitch, isotropically and anisotropically scaled sizes are considered. These scales sizes are compared with the design criteria, and accordingly a new best fit size is selected.
A research by Markets & Markets states that the FinFET market, which was valued at $4.91 billion in 2015, is expected to grow at a CAGR of 26.2% to touch $35.12 billion in 2022. The smartphone and wearables industries are expected to provide the most fillip to the growth of this semiconductor technology.
Samsung has begun producing 10nm FinFETs and has patented interesting methods in this technology space. One of this is described in its patent US 9412604.
And now, the Korean company has announced an ambitious plan to begin mass production of 10nm LPP chips by the end of 2017 and 10nm LPU wafers in 2018. The company is also working on 8nm and 6nm technologies.
Such a drop in feature sizes within ICs has begun a new race for semiconductor chip manufacturers to provide high levels of integration with lower power consumption. Partnerships, cross licensing agreements, M&As and contracts have already become the order of the day in developing FinFETs. With 8nm and 6nm chips on the anvil, it will be interesting to watch out for sleeker products coming the consumer’s way.