• iRunway
Reverse Engineering Solutions

We understand that a systematics analysis of different hardware components, how it is made, what it is made of and how it works under different scenario is key to proving infringement. We have a dedicated hardware and semiconductor practice led by technical experts with decades of experience in the semiconductor and IP industry. Our team of engineers have deep knowledge of advanced reverse engineering techniques and have expertise in multiple domains. Our reverse engineering solutions are designed to unearth critical evidence and ultimately help you win.

Cutting-edge Lab Infrastructure
and many more...

Finding Evidence of Use

iRunway provides an effective alternative to traditional models currently used to reverse engineer IC components and isolate evidence of use. We have expertise in several analytical techniques and will customize our solution depending on patents and the products under consideration.

Product Teardown

We can teardown all kinds of consumer electronic devices including smart phones, tablets and cameras to identify key components that set device performance such as processors, memories, sensors, communication modules and batteries. Once the device is disassembled, we can provide detailed documentation, identify and photograph the key components to find the required evidence that will assist in the infringement investigation.

Package Analysis

We can identify the packaging technology used in the device and analyze the structure and materials used in the package. Our engineers can determine the critical dimensions of the package and the materials used in die attach, wire bond and bumps. We can also analyze the state of the art in wafer level packaging such as 3D packages and packages using TSV’s.

Chip Analysis

In scenarios where identification and analysis of functional blocks of the IC is required, we will decapsulate the IC from its package and provide the floor plan of the IC identifying the major functional blocks. We can further probe and test the signals between major functional blocks and analyze how they interface with each other.

Back End of Line Analysis

Our engineers can perform high resolution SEM and TEM cross section imaging to identify the composition, structure and dimensions of the various layers in the device. We can provide dimensional and material analysis of back end of line (BEOL) layers such as metal interconnects, contacts, vias and interlayer dielectrics.

Front End of Line Analysis

We perform high resolution cross section imaging to identify and measure the critical process parameters of active and passive devices in the semiconductor substrate. Poly gates, gate oxides, implant doping levels, doping profiles, depth and composition of trenches and other substrate characteristics are measured. The front end of line (FEOL) analysis often includes physical and electrical characterization.

Circuit Extraction

We can completely extract the circuit and provide hierarchical circuit schematics, logic gate identification and the interconnections between various circuit blocks. We can also export the netlist information for subsequent simulations or analysis.

Sample Teardown Analysis – Samsung Galaxy S5 (SM-G900H)

We performed a complete teardown of a Samsung Galaxy S5 smartphone. Here are some x-ray and optical images of key components including memory, processor, microcontroller and sensors inside the smartphone.

Click here to view the teardown images

Sample Circuit Extraction

We extracted and analyzed in detail the circuit layout and hierarchical schematics of an IC in a printer device. Here are some images of the analysis including SEM of the metal layer, extracted circuit, circuit primitives, schematics and the netlist.

Click here to view the images of extracted circuit